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Synopsys' SystemVerilog Catalyst
program promotes the development and use of EDA tools,
verification IP and training services supporting the SystemVerilog
standard for design and verification.
Corporate members of the SystemVerilog Catalyst Program
may gain access to Synopsys' design and verification tools
including VCSTM, HDL CompilerTM,
the front-end language compiler for Design ComplierTM,
and LEDAR ® for the purposes of developing SystemVerilog-based
tools, ensuring their interoperability and providing support
for mutual customers. |
Tel +886-3-5794567
Fax +886-3-5799000
e-Mail 
